Akram Ben Ahmed

Senior Researcher

Intelligent Platforms Research Institute
National Institute of Advanced Industrial Science and Technology (AIST)
2-3-26 Aomi, Koto-ku, Tokyo JAPAN

Phone: +81-50-3522-9122
Email: akram (dot) benahmed (at) aist (dot) go (dot) jp

orcid.org/0000-0002-1253-8620

Profile

Akram BEN AHMED received his B.S. degree in Computer Science from the University of Sfax, Tunisia in 2009. He received his M.S.E and Ph.D. degrees in Computer Science and Engineering from the University of Aizu, Japan in 2012 and 2015, respectively. Upon his graduation, he joined the Amano laboratory at Keio University, Japan, as a postdoctoral researcher. He is currently a Senior Research Scientist at the National Institute of Advanced Industrial Science and Technology (AIST), Japan

Research Interests

Edge-computing communication
FPGA-based AI acceleration
On-chip interconnections
Reliability and Fault-tolerant systems
Ultra low-power embedded systems

Journals

N.-D. Nguyen, K. N. Dang, A. B. Ahmed, A. B. Abdallah, and X.-T. Tran, "NOMA: A Novel Reliability Improvement Methodology for 3-D IC-based Neuromorphic Systems," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 15, no. 11, pp. 2301-2313, Nov. 2025.
A. B. Ahmed, T. Hirofuchi, and T. Fukai, "Hardware Design and Evaluation of an FPGA-Based Network Switch Supporting Asynchronous Traffic Shaping for Time Sensitive Networking," in IEEE Access, vol. 12, pp. 123149–123165, Sept. 2024.
I. Ullah, A. B. Ahmed, K. Hironaka, K. Iizuka, and H. Amano, "A Multi-FPGA Implementation of FM-Index Based Genomic Pattern Search," IEICE Transactions on Information and Systems, vol. E106.D, no. 11, pp. 1783–1795, Nov. 2023.
N.-D. Nguyen, A. B. Ahmed, A. B. Abdallah, and K. N. Dang, "Power-Aware Neuromorphic Architecture With Partial Voltage Scaling 3-D Stacking Synaptic Memory," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 12, pp. 2016–2029, Dec. 2023.
K. N. Dang, A. B. Ahmed, A. B. Abdallah, and X.-T. Tran, "HotCluster: A Thermal-Aware Defect Recovery Method for Through-Silicon-Vias Toward Reliable 3-D ICs Systems," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 4, pp. 799–812, Apr. 2022.
M. Yamakura, R. Takano, A. B. Ahmed, M. Sugaya, and H. Amano, "A Multi-Tenant Resource Management System for Multi-FPGA Systems," IEICE Transactions on Information and Systems, vol. E104.D, no. 12, pp. 2078–2088, Dec. 2021.
K. Hironaka, K. Iizuka, M. Yamakura, A. B. Ahmed, and H. Amano, "Remote Dynamic Reconfiguration of a Multi-FPGA System FiC (Flow-in-Cloud)," IEICE Transactions on Information and Systems, vol. E104.D, no. 8, pp. 1321–1331, Aug. 2021.
K. N. Dang, A. B. Ahmed, Y. Okuyama, and A. B. Abdallah, "Scalable Design Methodology and Online Algorithm for TSV-Cluster Defects Recovery in Highly Reliable 3D-NoC Systems," in IEEE Transactions on Emerging Topics in Computing, vol. 8, no. 3, pp. 577–590, Oct. 2020.
K. N. Dang, M. C. Meyer, A. B. Ahmed, A. B. Abdallah, and X.-T. Tran, "A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip," in IEEE Access, vol. 8, pp. 59571–59589, Mar. 2020.
K. N. Dang, A. B. Ahmed, A. B. Abdallah, and X.-T. Tran, "TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 3, pp. 672–685, Mar. 2020.
H. Okuhara, A. B. Ahmed, J. M. Kühn, and H. Amano, "Asymmetric Body Bias Control with Low Power FD-SOI Technologies: Modeling and Power Optimization," IEEE Transactions on Very Large Scale Integration Systems, vol. 26, no. 7, pp. 1254–1267, July 2018.
H. Okuhara, A. B. Ahmed, and H. Amano, "Digitally Assisted On-chip Body Bias Tuning Scheme for Ultra Low-power VLSI Systems," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 10, pp. 3241–3254, Oct. 2018.
K. N. Dang, A. B. Ahmed, X.-T. Tran, Y. Okuyama, and A. B. Abdallah, "Scalable Design Methodology and Online Algorithm for TSV-Cluster Defects Recovery in Highly Reliable 3D-NoC Systems," IEEE Transactions on Emerging Topics in Computing, Oct. 2017 (In press).
K. N. Dang, A. B. Ahmed, Y. Okuyama, and A. B. Abdallah, "A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 11, pp. 3099–3112, Nov. 2017.
A. B. Ahmed, H. Matsutani, M. Koibuchi, K. Usami, and H. Amano, "Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-power Network-on-Chips Systems," IEICE Transactions on Electronics, vol. E99-C, no. 8, pp. 909–917, Aug. 2016.
A. B. Ahmed and A. B. Abdallah, "Adaptive Fault-Tolerant Architecture and Routing Algorithm for Reliable Many-Core 3D-NoC Systems," Journal of Parallel and Distributed Computing, vol. 93–94, pp. 30–43, July 2016.
A. B. Ahmed and A. B. Abdallah, "Graceful Deadlock-Free Fault-Tolerant Routing Algorithm for 3D-Network-on-Chip Architectures," Journal of Parallel and Distributed Computing, vol. 74, no. 4, pp. 2229–2240, Apr. 2014.
A. B. Ahmed and A. B. Abdallah, "Architecture and Design of High-Throughput, Low-Latency and Fault-Tolerant Routing Algorithm for 3D-Network-on-Chip," The Journal of Supercomputing, vol. 66, no. 3, pp. 1507–1532, Dec. 2013.

International Conferences

A. B. Ahmed, T. Hirofuchi, and T. Fukai, "EFCC: Ethernet Frame Crafter & Capture for TSN Research," The 50th IEEE Conference on Local Computer Networks (LCN2025), pp. 1-9, October 2025. (Best Paper Award Candidate)
A. B. Ahmed, T. Hirofuchi, and T. Fukai, "FPGA-Based Network Switch Architecture Supporting Credit Based Shaper for Time Sensitive Networks," 2024 IEEE 29th International Conference on Emerging Technologies and Factory Automation (ETFA), pp. 1–8, Oct. 2024.
A. B. Ahmed, R. Takano, and T. Hirofuchi, "Exploring the Potential of Error-Permissive Communication in Multi-FPGA-Based Edge Computing," 2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Penang, Malaysia, pp. 93–97, 2022.
Y. Yamauchi, A. B. Ahmed, K. Hironaka, K. Iizuka, and H. Amano, "Horizontal Division of Deep Learning Applications with All-to-All Communication on a Multi-FPGA System," 2020 Eighth International Symposium on Computing and Networking Workshops (CANDARW), pp. 277–281, Nov. 2020.
K. N. Dang, A. B. Ahmed, F. Z. Rokhani, A. B. Abdallah, and X.-T. Tran, "A Thermal Distribution, Lifetime Reliability Prediction and Spare TSV Insertion Platform for Stacking 3D-ICs," 2020 International Conference on Advanced Technologies for Communications (ATC), pp. 50–55, Oct. 2020.
M. M. I. Ullah, A. B. Ahmed, and H. Amano, "Implementation of FM-Index Based Pattern Search on a Multi-FPGA System," in F. Rincón, J. Barba, H. So, P. Diniz, and J. Caba (eds), Applied Reconfigurable Computing: Architectures, Tools, and Applications (ARC 2020), Lecture Notes in Computer Science, vol. 12083, Mar. 2020.
K. N. Dang, M. C. Meyer, A. B. Ahmed, A. B. Abdallah, and X.-T. Tran, "2D-PPC: A Single-Correction Multiple-Detection Method for Through-Silicon-Via Faults," 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 109–112, Nov. 2019.
K. Azegami, K. Musha, K. Hironaka, A. B. Ahmed, M. Koibuchi, and Y. Hu, "A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System," 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), pp. 328–333, Oct. 2019.
Y. Sun, A. B. Ahmed, and H. Amano, "Acceleration of Deep Recurrent Neural Networks with an FPGA Cluster," in Proc. of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART '19), pp. 1–4, June 2019.
K. N. Dang, A. B. Ahmed, and X.-T. Tran, "An On-Communication Multiple-TSV Defects Detection and Localization for Real-Time 3D-ICs," 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), pp. 223–228, Oct. 2019.
K. Hironaka, K. Iizuka, A. B. Ahmed, M. M. I. Ullah, Y. Yamauchi, Y. Sun, M. Yamakura, A. Hiruma, and H. Amano, "Demonstration of Flow-in-Cloud: A Multi-FPGA System," 2019 29th International Conference on Field Programmable Logic and Applications (FPL), pp. 417–418, Sept. 2019.
K. N. Dang, A. B. Ahmed, A. B. Abdallah, and X.-T. Tran, "TSV-IaS: Analytic Analysis and Low-Cost Non-Preemptive On-Line Detection and Correction Method for TSV Defects," 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 501–506, July 2019.
A. B. Ahmed, D. Fujiki, H. Matsutani, M. Koibuchi, and H. Amano, "AxNoC: Low-Power Approximate Network-on-Chips Using Critical-Path Isolation," in Proc. of the 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS-2018), Turin, Italy, pp. 44–51, Oct. 2018. (Best Paper Award Candidate)
A. B. Ahmed, H. Okuhara, H. Matsutani, M. Koibuchi, and H. Amano, "Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems," in Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC-18), Hanoi, Vietnam, pp. 146–153, Sept. 2018.
H. Okuhara, A. B. Ahmed, J. M. Kühn, and H. Amano, "Leveraging Asymmetric Body Bias Control for Low Power LSI Design," in Proc. of the IEEE COOL Chips XIX, Yokohama, Japan, pp. 1–3, Apr. 2017.
J. M. Kühn, A. B. Ahmed, H. Okuhara, H. Amano, O. Bringmann, and W. Rosenstiel, "MuCCRA4-BB: A Fine-Grained Body Biasing Capable DRP," in Proc. of the IEEE COOL Chips, Yokohama, Japan, pp. 1–3, Apr. 2016.
M. C. Meyer, A. B. Ahmed, Y. Tanaka, and A. B. Abdallah, "On the Design of a Fault-Tolerant Photonic Network-on-Chip," in Proc. of the IEEE International Conference on Systems, Man, and Cybernetics, Hong Kong, pp. 821–826, Oct. 2015.
M. C. Meyer, A. B. Ahmed, Y. Okuyama, and A. B. Abdallah, "FTTDOR: Microring Fault-Resilient Optical Router for Reliable Network-on-Chip Systems," in Proc. of the IEEE 9th International Symposium on Embedded Multicore SoCs (MCSoC-15), Turin, Italy, pp. 227–234, Sept. 2015.
A. B. Abdallah, M. Nakamura, A. B. Ahmed, M. C. Meyer, and Y. Okuyama, "Fault-Tolerant Router for Highly-Reliable Many-Core 3D-NoC Systems," in Proc. of the 3rd International Scientific Conference on Engineering and Applied Sciences (ISCEAS 2015), Okinawa, Japan, July 2015.
A. B. Ahmed, M. C. Meyer, Y. Okuyama, and A. B. Abdallah, "Adaptive Error- and Traffic-Aware Router Architecture for Electrical 3D Network-on-Chip Systems," in Proc. of the IEEE 8th International Symposium on Embedded Multicore SoCs (MCSoC-14), Aizu-Wakamatsu, Japan, pp. 197–204, Sept. 2014.
A. B. Ahmed, A. B. Ahmed, and A. B. Abdallah, "Deadlock-Recovery Support for Fault-Tolerant Routing Algorithms in 3D-NoC Architectures," in Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC-13), Tokyo, Japan, pp. 67–72, Sept. 2012.
A. B. Ahmed, T. Ochi, S. Miura, and A. B. Abdallah, "Run-Time Monitoring Mechanism for Efficient Design of Application-Specific NoC Architectures in Multi/Manycore Era," in Proc. of the 6th International Workshop on Engineering Parallel and Multicore Systems, Taichung, Taiwan, pp. 440–445, July 2013.
A. B. Ahmed and A. B. Abdallah, "Low-Overhead Routing Algorithm for 3D Network-on-Chip," in Proc. of the 3rd International Conference on Networking and Computing (ICNC-12), Okinawa, Japan, pp. 23–32, Dec. 2012.
A. B. Ahmed and A. B. Abdallah, "LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture," in Proc. of the IEEE 6th International Symposium on Embedded Multicore SoCs (MCSoC-12), Aizu-Wakamatsu, Japan, pp. 167–174, Sept. 2012.
A. B. Ahmed, K. Mori, and A. B. Abdallah, "ONoC-SPL Customized Network-on-Chip (NoC) Architecture and Prototyping for Data-Intensive Computation Applications," in Proc. of the 4th International Conference on Awareness Science and Technology (iCAST-2012), Seoul, South Korea, pp. 257–262, Aug. 2012.
A. B. Ahmed, A. B. Abdallah, and K. Kuroda, "Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multi-Core SoC," in Proc. of the 5th International Conference on Broadband and Wireless Computing, Communication and Applications (BWCCA-2010), Fukuoka, Japan, pp. 67–73, Nov. 2010. (Best Paper Award)